The present invention relates to a memory apparatus used for a microprocessor or the like.
In a mainframe computer or other computer systems including a microprocessor, a cache memory apparatus is used for holding a part of the contents of a main memory between a central processing unit and the main memory to improve the operating speed.
The cache memory apparatus finds various applications. Some of them include the data cache or the instruction cache. These cache memory apparatuses may be configured of what is called a CAM (Content Addressable Memory). In the CAM, it is decided whether a search address is matched with an address stored in a first memory cell array (tag array), and if matching, a separate second memory cell array (data array) is accessed thereby to read the data or instruction at high speed.
Another application is an address translation cache for supporting a virtual memory system which is a cache memory apparatus generally called TLB (Translation Lookaside Buffer). This TLB is supplied with a logical address of data required by the central processing unit or the like as a search address, and matching with the content of the first memory cell array (LA) already holding the logical address is detected. It is also decided whether there is a physical address corresponding to the second memory cell array (PA) holding a physical address. If they match with each other, the result (what is called hit information) of decision and a corresponding physical address are produced as an output.
As described above, a cache memory apparatus requires the function of detecting the match between search data and data stored in a first memory cell and the function as a selector for producing the corresponding data stored in a second memory cell array on the basis of a match signal.
A well-known means for realizing the selector function and the function of match detection includes a match detection circuit and a selector circuit disclosed in Nikkei Micro-devices, Apr. 1987, pp. 75 to 90 (hereinafter referred to as "the first prior art") and The Transaction of the Institute of Electronics, Information and Communications in Japan 88/10, Vol. J71-C No. 10, pp. 1442-1449 (hereinafter referred to as "the second prior art").